enbarchon

I was always curious about the kind of math and calculations that go into launch, and navigation to and from a distant point in space. Is this something that is planned out in advance, or based on feedback and corrections. Do you factor in things like the position of the moon, and what effect its gravity will have on potential flight paths? When returning to the earth how much thought goes into the rotation of the planet with respect to the returning capsule. Dunno, just something I always wondered about.

It is extremely difficult to design integrated circuits because they have to be designed as 2 Dimensional layers, stacked together in the third dimension. The total price of the device is greatly increased with additional layers as the chance of defects increases with each added layer (this was discussed elsewhere). As a result they build all the circuit elements on a single layer.

I am neglecting factors such as the depth of silicon needed to make an actual transistor, and the difficulty of depositing pure single crystalline in higher layers to have transistors stacked on top of transistors. There is also factors like heat dissipation, where "buried" transistors would be hotter then "surface" transistors and therefore would have different electrical characteristics that could affect device operation. These sorts of factors are a little too difficult to explain in a reddit post.

In conclusion it saves a lot of money, it is easier to design, and operates in a more consistent fashion to design planar circuits, instead of 3 Dimensional stacked transistors. Currently the "savings" from slightly shorter signal paths is no where near enough to warrant this type of research and design.

Another factor I didn't mention has to do with metal interconnecting, or in essence connecting wires or pins (such as those visible when you remove and look at the bottom of a CPU) to these 22nm transistors. There are many many layers (not exactly sure how many, I am sure this is an Intel secret) of metal and insulating layers that build up from the transistor level to the actual connection level. These would also make it very difficult to implant additional transistors into 3 Dimensional patterns. A photo showing an example of these interconnects is here: http://www.azom.com/work/5s7YmsW1KtzZ2ts1FTv0_files/image005.jpg.

Source: Am Nanotechnology Engineering Student, hoping to work at Intel some day.

Thanks a lot! Seems like there is a lot more thought that goes into it then I expected.